1. Field of the Invention
The present invention relates to a communication data receiver and a buffer control method, in particular to a data receiver that transfers data from a physical layer via a buffer memory to an ATM layer, and to a buffer control method.
2. Description of the Related Art
FIG. 12 provides a block diagram indicating the configuration of the conventional communication data receiver. In FIG. 12, a received cell 801 is entered to a cell synchronous circuit 802 which in turn generates a cell synchronizing signal 803 and a cell start signal 804. Further, the cell synchronous circuit supplies a first-in first-out type buffer memory with write data 805. The cell synchronizing signal 803 and the cell start signal 804 are entered to an AND circuit 806. An output signal 807 from the AND circuit 806 sets an SR flip flop 817.
A write stop signal 811 as the control signal used to stop programming FIFO buffer memory 857, an overflow detection signal 826 output upon the detection of an overflow, and a 52-detection signal 814 are entered to an OR circuit 873. The SR flip flop 817 is reset by an output signal 874 from the OR circuit 873. A write restart signal used to control the restart of programming the FIFO buffer memory 857, and the output signal 807 from the AND circuit 806 may be entered to a set terminal S of the SR flip flop 817.
A write signal 818 used to control the programming of the FIFO buffer memory is output from the SR flip flop 817. A counter 820 is incremented by the write signal 818. An output signal 821 from the counter 820 is entered to a 52-detection section. When the counter 820 reads a value of "52", the 52-detection signal 814 is output. The counter 820 is reset by the 52-detection signal 814.
A counter 855 is incremented by the write signal 818 and reset by the overflow detection signal 826. A counter 853 is incremented when a read signal 819 is active, and reset by the overflow detection signal 826. Signals from the counters 855 and 853 are output as a write address 856 and a read address 854 for the FIFO buffer memory 857, respectively.
A counter 823 is incremented by the write signal 818, decremented by the read signal 819, and reset by the overflow detection signal 826. An overflow detection section 825 generates the overflow detection signal 826 in response to an output signal 824 from the counter 823. The conventional data receiver shown in FIG. 12, each of the flip flop and counters is operated by a system clock clk.
FIG. 13 provides a timing chart helping understand the normal operation of the conventional data receiver. FIG. 14 provides a timing chart helping understand the abnormal operation of such data receiver, i.e. an overflow occurring in the FIFO buffer memory 857.
FIGS. 12, 13 and 15 are used to explain the normal operation of the conventional data receiver. Received data 801 is composed of ATM cells, each of which comprises 53 bytes of data, 5 bytes of a header section and 48 bytes of payload section, as shown in FIG. 15.
The cell synchronous circuit 802 performs CRC operation on five bytes of received data 801. If the result is "0", the cell synchronous circuit regards the five bytes as the header of the ATM cell. Further, the cell synchronizing signal 803, the cell start signal 804, and write data 805 are generated in the timing shown in FIG. 13. The cell synchronizing signal can also be generated when a series of cells of the cell start signal 804 is detected.
When the cell synchronizing signal 803 and the cell start signal 804 become active, the output signal 807 from the AND circuit 806 becomes active, with the SR flip flop 817 set and the write signal 818 becoming active.
The counter 820 is incremented by a rise in the system clock clk when the write signal 818 is active. The counter 820 is reset by the 52-detection signal 814 when it reads a count value of "52". The 52-detection signal 814 resets the SR flip flop 817 via the OR circuit 873. When the FIFO buffer memory 857 is programmed with 53 bytes of write data 805, the 52-detection signal 814 attempts to inactivate the write signal 818.
In the example illustrated in FIG. 13, the cell start signal 804 becomes active in the same timing as the 52-detection signal 814. Further, the output signal 807 from the AND circuit 806 providing the logical product of the cell start signal 804 and the cell synchronizing signal 803 becomes active. In addition, as the SR flip flop 817 is set initially, the write signal 818 is held active (high in FIG. 13). This is because a series of ATM cells (input data 801) is entered.
The write address 856 given from the counter 855 is incremented by a rise in the system clock clk when the write signal 818 is active. The read address 854 given from the counter 853 is incremented by a rise in the system clock clk when the read signal 819 is active.
A counter 23 controls the number of bytes of data stored in the FIFO buffer memory 857. The counter 823 is incremented by a rise in the system clock clk when the write signal is active, and decremented by a rise in the system clock clk when the read signal 819 is active.
Then, FIGS. 12 and 14 are used to explain the abnormal operation of the conventional data receiver, i.e. an overflow occurring in the FIFO buffer memory 857. This explanation assumes that the size of the FIFO buffer memory 857 is four cells (=212 bytes) and that data is written to and read from the FIFO buffer memory 857 as if the data receiver were operated normally. When the counter 23 reads a value of "212" (indicating that the FIFO buffer memory 857 is filled), the overflow detection section 825 generates the overflow detection signal 826 as soon as the write signal 818 becomes active.
The generation of the overflow detection signal 826 is regarded as the occurrence of a fatal error, with the counters 853, 855 and 823 and the SR flip flop 817 reset. Thus, the write operation is stopped and the circuit is initialized. Then, a new ATM cell whose header has been detected restarts to be written into the FIFO buffer memory 857, and up to four cells of data are discarded.
The above conventional data receiver is such that, triggered off by the occurrence of an overflow in the FIFO buffer memory 857, the circuit used to control the buffer memory including write and read addresses is reset. This means that all the data corresponding to the size of the FIFO buffer memory 857 is discarded. The result is that high-order processing requires the resending of a large amount of data. Thus, data transfer is adversely affected significantly.
The problem consists in the fact that new input data is discarded until the release of a detected overflow. Hence, significant data may be discarded and insignificant data may not be discarded. For example, Japanese Patent Application Laid-open No. 242348/1992 comes up with countermeasures for figuring out the problem. Such countermeasures are characterized by the configuration shown in FIG. 16, providing a process for discarding excessive input data for packet communication and other highly efficient communication.
The feature of the means revealed in FIG. 16 consists in the detection of the arrival of input data by a data arrival detection circuit 981. Input data that cannot be output by the next overloaded process is stored in a buffer memory 982. A loss table 986 developed by algorithm composed of input ports, past discarded data and test patterns provides against an overflow of the buffer memory 982. The loss table is used by a loss controller 985 to control a writing counter (WCTR) 983 and a reading counter (RCTR) 984. This control allows the discard of less significant data in the buffer memory 982 and the accumulation of past discards for each input port 987. Thus, data in an input port that has undergone less discard is discarded first.
However, the data discard process shown in FIG. 16 cannot judge the importance of data before transferring data to the ATM layer processor.
Further, Japanese Patent Application Laid-open No. 58646/1992 comes up with a new buffer control means. The buffer control means adds the pre-counted data length of received packet data for storage into a transmission buffer memory and uses such data length to update a reading address during an overflow. The addition of data indicating data length requires a corresponding buffer memory, however.